Using TAMS 71622 with HP-UX 10.20

The manual for the 71622 refers to comments in the hwconfig.cf file to provide information on configuring the parameters. In many cases, that information was not included in that file for 10.20, making the configuration impossible. The information is included here, which can be appended as comments to the file to remedy the situation. The file location is under
/etc/opt/sicl.

If using 'iosetup' to configure the card, there are Location and Address parameters that can be entered. The Location is just the PCI slot number, and Address gets mapped to the integer representing the signal to be used by the driver. This should be set to "0". It is generally easier to edit hwconfig.cf manually than to use 'iosetup' with this card.

#
# SICL Driver Configuration File for TAMS61622 PCI GPIO card
#
# TAMS61622 card is compatible with HP E2074/5 GPIO
# and TAMS60622 GPIO cards
#

#
# TAMS61622 Card (PCI GPIO Interface Card):
# <lu> <symname> t61622 <slot_num> <sig> <polarity> <mode> <read_clk> <delay>
#
# where:
# <slot_num> - For 10.x users, the PCI slot number.
# For 11.x users, the rotary switch positon.
# <sig> - Selects an HP-UX signal to be used by t61622 driver
# for interrupts.
# The value must be in decimal format and must be 0
# or one of the values defined in signal.h header file.
# Allowed signals are SIGIOT, SIGEMT, SIGUSR1, SIGUSR2
# SIGIO or SIGURG. A value of 0 sets the default signal
# which is SIGURG.
# A signal is used by t61622 driver to notify applications
# about kernel events. You can select a signal to be used
# by the driver to avoid conflicting with other software.
# <polarity> - The logic polarity of various interface lines.
# A "0" sets active low polarity; a "1" sets active high.
# Each bit controls the polarity of one function:
#
# +------- 0=do NOT use pullup resistors 1=DO use them
# |+------ Data Out
# || +---- PSTS
# || |
# 0b000000-- PCTL
# | |
# | +--- PFLG
# +----- Data In
#
# <mode> - Configures handshake and data port mode.
# First (left) hex digit configures the data port:
# HP 98622 compatibility mode:
# 0 = No DOUT clear at reset
# 1 = Clear DOUT at reset
# Enhanced (bi-directional DINs) data port:
# 2 = No DOUT clear at reset
# 3 = Clear DOUT at reset
# Second (right) hex digit selects the PFLG/PCTL
# handshake mode:
# 0 = Full handshake
# 1 = Pulse handshake
# 2 = Async-Write/Pulse-Read handshake
# For example, 0x20 sets:
# enhanced mode, no DOUT clear, full handshake
#
# t61622 provides a way of specifying mode in binary:
#
# +------- 0=do NOT clear AUX 1=clear AUX at reset
# |+------ 0=do NOT clear DOUT 1=clear DOUT at reset
# ||
# 0b000000-- data_in handshake: 0=full 1=pulse
# |||
# |++--- data_out handshake:
# | 00=full 01=pulse 10=11=async
# |
# +----- data_out enhanced bi-directional mode:
# 0=compatibility_out 1=enhanced_out
#
# Note that when using binary notation for mode, more
# control is possible (combinations not possible with hex).
# Care should be taken when this special handshake
# and data port mode configurations are used.
#
# <read_clk> - Determines when data input registers are latched.
# First hex digit is for upper (most significant) byte.
# Second hex digit is for lower byte.
# 0 = When register is read
# 1 = At Busy edge
# 2 = At Ready edge
#
# <delay> - The delay (settling time) from data write to PCTL set:
# 0 = 200 nanoseconds
# 1 = 400 nanoseconds
# 2 = 700 nanoseconds
# 3 = 1.2 microseconds
# 4 = 2 microseconds
# 5 = 5 microseconds
# 6 = 10 microseconds
# 7 = 50 microseconds
# t61622 provides alternative delay configuration method.
# The delay may be expressed in nanoseconds or in
# microseconds. If the delay is expressed in nanoseconds
# the decimal value representing delay should be suffixed
# with "ns". If the delay is expressed in microseconds
# the decimal value representing delay should be suffixed
# with "us". Decimal point is allowed.
# Minimum delay is 90ns and maximum delay is 245us.
# Examples: 150ns, 2500ns (same as 2.5us), 1.15us, 90us
#
#
# t61622 GPIO Card on slot 1
#22 gpio t61622 1 0 0b00000 0x00 0x00 2 # Card in slot #1
#
# Uncomment the following lines for the 2nd thru 4th card:
#23 gpio2 t61622 2 0 0b00000 0x00 0x00 450ns # Card in slot #2
#24 gpio3 t61622 3 0 0b00000 0x00 0x00 2.1us # Card in slot #3
#25 gpio4 t61622 4 0 0b00000 0x00 0x00 3.5us # Card in slot #4
#
#


Home \| Products \| Support \| How to Order \| Contact Us \| Search