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This document explains how reliable data transfer can be
accomplished with TAMS GPIO (61622/71622/81622) cards with long cables using full
handshake mode at high data rates. With the noise and crosstalk
characteristics common in long cables, care must be taken to provide
adequate noise immunity in the circuitry. Cables have moderately low
impedance characteristics (approx. 100 ohms), which require good drive
capability and attention to impedance matching to avoid reflections that
can cause logic faults.
If these recommendations are followed, it is possible to
reliably drive high-quality cables (such as those available from TAMS)
at moderately high rates (in the megahertz area) and at lengths up to 15
feet. Use of longer cables is not recommended, and using shorter lengths
when feasible will minimize the problems encountered while maximizing
the data rates achievable. Use the minimal length cable that is suitable
for your application.
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The +5 signal line is subject to considerable
crosstalk in the cable. If used in the interface, be sure to bypass
adequately (22 uF tantalum suggested). This line has limited current
capability, and should not be used to supply more than .5 amps for
any purpose. If current from the interface is fed back into the
computer through this line, there exists the possibility that the
computer power supply could crowbar and fail to power up.
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The PCTL/PFLG handshake lines are critical for
insuring reliable data transfer. It is recommended that the PCTL
line should be terminated with a 150/220 ohm powered resistor
divider, with the 150 ohm resistor connected to +5 and the 220 ohm
to ground. If powered from +5 from the cable, observe item 1).
Hysteresis on the receiver used for this line may be helpful for
minimizing the effects of noise.
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The pullup capability of outputs on the gpio card is
limited to 4.7K pullup resistors. This is not suitable for driving
significant lengths of cable at the highest data rates, and thus the
recommendation in item 2) for the handshake line. The output data
lines will have slow rise times without external resistors being
added, but this is not a problem if sufficient PCTL delays can be
used to allow adequate settling time. 800 ns is generally sufficient
if only the on-board 4.7K pullups are used. Shorter PCTL times are
possible if powered termination is used for all output lines.
Current drive capability on output lines is limited to 40 ma, which
must be considered if modifying the suggested resistor values.
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The two handshake lines frequently are adjacent in
the cabling and subject to substantial crosstalk. If they are of the
same polarity, then the crosstalk may create problems. If PCTL is
high-clear and PFLG is low-ready, then crosstalk from PCTL to PFLG
will cause minimal problems.
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If doing reads, the external circuitry must provide
any additional delay needed for data settling time. If PFLG is not
delayed with respect to PCTL at the interface, transfer rates of up
to 5 mega-transfers per second can be seen. Some time delay will
almost certainly need to be inserted by the circuitry in order to
allow adequate settling time on the data lines.
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Pullup resistors are programmable on the 61622/71622
interface cards. These should normally be enabled, unless specific
applications require otherwise.
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Additional information concerning use of the 61622
card is available in the help file included with the driver
installation.
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